EDN

Backplane tutorial: RapidIO, PCIe and Ethernet

While there are many ways to connect components in embedded systems, the most prominent are the high speed serial standards of Ethernet, PCI Express, and RapidIO. All of these standards leverage ...
GitHub

intro_pcie_x1_xdma_bram_blockdesign.md

Lane Width 可以自由指定，因为 NetFPGA 的 PCIe 为 x8，我们可以取 x1, x4, x8 。本例中取 x1 。 Maximum Link Speed 代表的是 PCIe 的速率，可以自由指定，2.5 GT/s 代表 PCIe Gen1， 5.0 GT/s 代表 PCIe Gen2，8.0 GT/s 代表 PCIe Gen3 。本例中取 5.0 GT/s Reference ...
GitHub

pcie_dw_mvebu.c

#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) #define PCIE_LINK_STATUS_WIDTH_OFF 20 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) /* Resizable bar ...
LinkedIn

Xilinx DMA PCIe tutorial-Part 2

In part 1 of my tutorial I've gone over the basic issues related to DMA. I covered the various solutions applicable (the ones I've found. I'm sure there's more). In the following part 2 of my tutorial ...
LinkedIn

Xilinx DMA PCIe tutorial-Part 1

This document is a thorough tutorial on how to implement a DMA controller with Xilinx IP. My idea was to write a comprehensive guide with all Do’s and Don’ts related to the implementation of DMA ...