GitHub

AES Hardware Verification — SystemVerilog + DPI-C + Python

This project demonstrates hardware/software co-simulation between a SystemVerilog testbench, a C++ DPI layer, and a Python reference model. The goal is to verify a hardware AES-128 ECB encryption core ...
GitHub

RISC-V CPU Core — UVM-Based ISA Compliance Verification

hw/rtl/ └─ riscv_core_top_stub.sv # DUT (or a stub) dv/ ├─ include/ │ └─ riscv_defs.svh # typedefs/defines ├─ if/ │ └─ commit_if.sv # commit/retire interface ├─ env/ │ └─ ref_env_pkg.sv # env + test ...