IEEE

Chip design for turbo encoder module for in-vehicle system

Abstract: This paper studies design and implementation of the Turbo encoder to be an embedded module in the in-vehicle system (IVS) chip. Field programmable gate array (FPGA) is employed to develop ...
EDN

Xilinx Meets Performance Requirements of LTE Wireless Systems With New LogiCORE Turbo Encoder and Decoder Solu

Xilinx Meets Performance Requirements of LTE Wireless Systems With New LogiCORE Turbo Encoder and Decoder SolutionsDelivers 5X throughput boost to developers of next-generation wireless systems ...
Electronic Design

Turbo Encoder Coprocessor Supports 3GPP HSDPA

Touted as the industry's most cost-effective turbo encoder co-processor available to support the recently established 14.4 Mb/s third generation partnership project (3GPP) high-speed downlink packet ...
EDN

3GPP turbo encoder co-processor

San Jose, Calif. — A MegaCore intellectual property (IP) block has been developed for the Cyclone family of CPLDs that can offload 3GPP high-speed downlink packet access (HSDPA) turbo encoding from a ...