Semiconductor Engineering

Freeing Up Near-Memory Capacity For Cache Using Compression Techniques In A Flat Hybrid-Memory Architecture

A technical paper titled “HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory” was published by researchers at Chalmers University of Technology and ZeroPoint Technologies.
Semiconductor Engineering

Adaptive RISC-V Cache Architecture for Near-Memory Extensions (Politecnico di Torino, EPFL)

A new technical paper titled “ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions” was published by researchers at Politecnico di Torino and EPFL. Abstract “Modern data-driven ...
Design-Reuse

A Re-Usable Level 2 Cache Architecture

This paper presents the architecture of a high performance level 2 cache capable of use with a large class of embedded RISC cpu cores. The cache has a number of novel features including advanced ...
GIGAZINE

An expert explains in an easy-to-understand way what CPU cache memory is

When talking about CPU specifications, in addition to clock speed and number of cores/threads, ' CPU cache memory ' is sometimes mentioned. Developer Gabriel G. Cunha explains what this CPU cache ...
Nature

Data Prefetching Techniques in Computer Architecture

Data prefetching has emerged as a critical approach to mitigate the performance bottlenecks imposed by memory access latencies in modern computer architectures. By predicting the data likely to be ...