GitHub

armleo/Sdr-Viterbi-Decoder-in-Verilog

The Viterbi algorithm is renowned as a maximum likelihood (ML) decoding technique for convolutional codes. The path memory unit in an (n,k,m) Viterbi Decoder is responsible for keeping track of the ...
GitHub

kishore07062005/Implementation-of-Decoder-and-Encoder-using-Verilog-HDL

To design and implement 3 X 8 decoder and 8 X 3 encoder circuit using Verilog HDL and verify its truth table. The combinational circuit that changes the binary information into 2N output lines is ...
IEEE

Design of low density parity check decoder using Min-Sum algorithm

Abstract: Low density parity check (LDPC) code has received more attention due to their excellent error correcting performance capabilities. An LDPC code can be ...