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Verilog HDL project to simulate a 7-segment display decoder using ModelSim

Notifications You must be signed in to change notification settings This project demonstrates the design and simulation of a 7-segment display decoder using Verilog Hardware Description Language (HDL) ...
GitHub

CS6230 Viterbi Decoder Project

This project implements a hardware Viterbi decoder in Bluespec SystemVerilog (BSV) for the CS6230 Computer-Aided Design for VLSI course. The decoder solves the Hidden Markov Model (HMM) inference ...