GitHub

This repository contains four laboratory assignments covering combinational circuits, sequential logic with Verilog, FPGA implementation, and memory systems.

Simplify and implement a circuit with inputs A1, A0, B1, B0 and outputs X, Y, Z using only 74LS ICs in Logisim. Learn Boolean algebra simplification and basic gate usage. Lab 2: Multiplexers, Decoders ...
TechRepublic

Comparison Between Serial Adder and Parallel Adder

Basically in digital system there are two type of circuit: combinational logic circuit and sequential logic circuit. When the authors talk about combinational circuit, this circuit is that circuit of ...
IEEE

Efficient methodology for testable reversible sequential circuit design

Abstract: Due to ultra-low power consumption, demand of reversible logic has been increased. In this article, primary intention is to not to increase the garbage output, area and delay to introduce ...
IEEE

DE2: SAT-Based Sequential Logic Decryption with a Functional Description

Abstract: Logic locking is a promising approach to protect the intellectual properties of integrated circuits. Existing logic locking schemes assume that an adversary must possess a cycle-accurate ...